Data processing systems are used in myriad applications which touch virtually every aspect of life. In applications where the data processing system uses battery power for any substantial length of time, it is particularly desirable to be able to minimize the power consumption of the data processing system. Examples of systems wherein battery power is used for substantial periods of time include portable data processing systems such as notebook and sub-notebook computer systems, and data processing systems which are employed in remote locations, hazardous weather areas, or earthquake prone areas.
In applications which require high performance from a data processing system, the high performance requirement often presents a heat dissipation problem. As a result, most high performance data processing devices use expensive packages such as ceramic pin grid arrays in order to provide heat dissipation capabilities adequate to avoid overheating the data processing device.
In addressing the power management issues presented by the above-described circumstances, it is known that the power dissipation of a data processing system having a fixed operating voltage is given by the following equation: EQU P=CV.sup.2 f,
where P is the power dissipated, C is the effective power dissipation capacitance, V is the operating voltage and f is the effective transition frequency. Thus, the dissipated power P can be reduced by reducing the effective transition frequency f.
In one known approach to reducing the effective transition frequency f, a data processing device can divide down its own clock frequency in response to an external stimulus. For example, one known conventional RISC microprocessor has a reduced power mode of operation wherein it responds to an external stimulus to reduce its internal clock frequency by 75%. As noted above, however, the data processing system must be capable of providing the data processing device, in this case the RISC microprocessor, with the necessary external hardware/software intervention to cause the microprocessor to switch among its available power-conserving states.
FIG. 1 illustrates one example of the above-described conventional approach wherein a microprocessor (CPU 11 in FIG. 1) responds to external stimulus from elsewhere in the data processing system 13 to switch into a power-conserving state, for example by reducing its internal clock frequency by 75%. The external stimulus is provided to CPU 11 in FIG. 1 in the form of the control CPU clock signal. The control CPU clock signal is output from an activity monitor 15 which receives system activity information from various components of the data processing system 13. Thus, each illustrated component of the data processing system 13, namely, the graphics controller, the hard-disk drive, the floppy drive, the keyboard, the mouse, the serial interface unit, the parallel interface unit, and the bus interrupt controller provides the activity monitor 15 with information regarding its own individual activity. The activity monitor 15 includes an activity meter 17 which maintains a record of the activity of each system component. When the system activity, as represented by the activity inputs from the individual system components, is sufficiently low, the activity monitor 15 provides CPU 11 with the control CPU clock signal, and the internal clock frequency of the CPU 11 is reduced in response to this control CPU clock signal. The basic idea of the system of FIG. 1 is that, when the system activity is sufficiently low, the CPU activity will also be correspondingly low, so that the clock frequency of the CPU can be reduced without substantially impairing system performance.
However, the present invention recognizes that, as more cache is provided on-chip with the microprocessor, it is more difficult to draw conclusions about the CPU activity by observing the activity of the external system components. For example, although the individual system components may appear to be idle, the CPU itself may well be busy due to increased utilization of on-chip cache. Under these circumstances, the activity monitor 15 would direct the CPU 11 to reduce its clock frequency, thus disadvantageously increasing the time required for the CPU to perform its current, albeit externally undetectable, tasks. It is desirable therefore to provide a power management technique which is capable of detecting internal CPU activity and which controls the CPU for high performance when necessary, but automatically reduces the power consumption of the CPU as conditions warrant.
The present invention provides a CPU-driven power management technique capable of detecting internal CPU activity and controlling the CPU for high performance when necessary, while automatically reducing the CPU's power consumption as conditions warrant.